Digital Relay Logic Interlocking for Selective Tripping

Industry Applications

Urban MV distribution, utility smart grid upgrades, industrial campuses with cogeneration, naval shipboard power systems

Key Standards

IEC 61850-7-420 (functional modeling), IEEE C37.223 (application guide), EN 62271-306 (GIS interlocking)

Typical Scale

Deployed across 200+ substations in ERCOT; average logic size: 12–28 rungs (FBD), <5 kB configuration memory

Cybersecurity Requirement

Mandatory GOOSE authentication per IEC 62351-6; logic signature verification required for NERC CIP-010 compliance

⚠️ Why It Matters

1

Fault occurs in feeder segment

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2

Without interlocking, multiple breakers trip unnecessarily

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3

Extended outage affects non-faulted customers and critical loads

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4

Loss of system resilience and regulatory non-compliance (e.g., IEEE 1547, EN 50160)

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5

Increased SAIDI/SAIFI metrics and customer dissatisfaction

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6

Higher operational cost from manual restoration and incident investigation

📘 Definition

Digital Relay Logic Interlocking (DRLI) is a coordinated protection scheme that uses programmable logic within microprocessor-based relays to enforce selective tripping by dynamically enabling or inhibiting trip outputs based on real-time status of upstream/downstream devices, communication signals (e.g., GOOSE), and pre-defined logic sequences. It extends conventional time- and current-based coordination by incorporating state-aware, event-driven logic to resolve ambiguities in fault location, especially in meshed, looped, or bidirectional distribution networks.

🎨 Concept Diagram

AI-generated illustration for visual understanding

💡 Engineering Insight

Interlocking logic is not a substitute for proper time-current coordination—it is its precision scalpel. In practice, the most robust schemes use *layered selectivity*: TCC provides the coarse filter, directional elements add spatial discrimination, and logic interlocking resolves edge cases (e.g., backfeed during maintenance). Always verify interlock behavior under worst-case timing skew: assume one relay is 15 ms behind due to firmware version mismatch or temperature drift.

📖 Detailed Explanation

At its core, digital relay logic interlocking replaces fixed time delays with conditional decisions—like asking 'Is the downstream breaker already open?' before allowing an upstream trip. This requires relays to exchange status and fault data reliably, typically via IEC 61850 GOOSE, turning protection from isolated devices into a collaborative network.

As systems grow more complex—especially with distributed energy resources (DERs), microgrids, and automated switching—the logic must handle dynamic topology changes. Modern implementations embed state machines (e.g., 'Normal', 'Loop-Closed', 'Islanded') where interlock rules adapt in real time. This demands rigorous validation: a relay may pass unit testing but fail when 12 GOOSE inputs arrive within 2 ms of each other during a bus fault.

Advanced applications include adaptive interlocking using synchrophasor inputs (IEEE C37.118) to detect power flow reversal at sub-cycle resolution, or machine-learning-augmented logic that updates blocking thresholds based on historical fault statistics. However, such sophistication must comply with IEC 62443 cybersecurity requirements and be fully traceable—every logic branch must map to a functional requirement in the protection specification (per IEEE C37.223).

🔄 Engineering Workflow

Step 1

Step 1: Map protection zones and define zone boundaries using single-line diagram and device CT/VT ratios

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Step 2

Step 2: Perform time-current coordination study (TCC) to establish baseline selectivity gaps

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Step 3

Step 3: Identify interlocking triggers (e.g., downstream fault detection, breaker position status, DER export flag)

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Step 4

Step 4: Program relay logic using IEC 61131-3 (LD/FBD) or vendor-specific logic builder; validate in hardware-in-loop (HIL) simulator

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Step 5

Step 5: Commission with sequential injection testing (primary & secondary) and GOOSE message trace analysis

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Step 6

Step 6: Document logic diagrams, signal tags, and failure mode & effects analysis (FMEA) per IEC 61508 SIL2 requirements

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Step 7

Step 7: Integrate into SCADA alarm matrix and configure automated logic health monitoring (e.g., GOOSE heartbeat loss alarms)

📋 Decision Guide

Rock/Field Condition	Recommended Design Action
Radial feeder with single upstream source and no distributed generation	Use simple directional overcurrent interlocking: downstream relay blocks upstream trip if fault current flows toward load.
Looped MV network with two independent sources and auto-reclose capability	Implement dual-state GOOSE interlocking with source-identification tags and synchro-check enforced before reclosing.
Feeder with rooftop PV <500 kW and anti-islanding protection enabled	Add voltage/frequency ride-through (VRT/FRT) status input to interlock logic—disable blocking if islanding detected.
Substation with legacy electromechanical breakers and modern digital relays	Use hardwired contact interlocking (not GOOSE); limit logic to binary enable/disable with 100 ms safety margin.

📊 Key Properties & Parameters

Trip Logic Delay

20–120 ms

Programmable time window during which a relay waits for a blocking signal before initiating trip output.

⚡ Engineering Impact:

Determines minimum selectivity margin; too short risks nuisance tripping, too long compromises fault clearance speed.

GOOSE Message Latency

3–15 ms (IEC 61850-9-2 compliant systems)

End-to-end transmission delay for Generic Object Oriented Substation Event messages used for inter-relay signaling.

⚡ Engineering Impact:

Directly limits achievable coordination speed; latency >25 ms breaks sub-cycle selectivity in fast-acting schemes.

Logic Execution Cycle Time

1–10 ms

Maximum time required for a relay’s embedded PLC engine to scan, evaluate, and update all configured logic equations.

⚡ Engineering Impact:

Bottlenecks complex interlocking sequences; cycle times >5 ms restrict implementation of cascaded or adaptive logic.

Blocking Signal Hold-off Time

50–200 ms

Minimum duration a relay must maintain blocking state after receiving a valid inhibit signal to prevent chattering or race conditions.

⚡ Engineering Impact:

Prevents false re-closure or premature trip release during transient communication glitches or relay synchronization drift.

📐 Key Formulas

Minimum Selective Interlock Time Margin

Δt_min = t_upstream − t_downstream − t_GOOSERx − t_logic − t_safety

Calculates the minimum time buffer needed between upstream and downstream relay operations to guarantee selectivity under worst-case timing.

Variables:

Symbol	Name	Unit	Description
Δt_min	Minimum Selective Interlock Time Margin	s	Minimum time buffer needed between upstream and downstream relay operations to guarantee selectivity under worst-case timing
t_upstream	Upstream Relay Operating Time	s	Time taken by the upstream protective relay to operate
t_downstream	Downstream Relay Operating Time	s	Time taken by the downstream protective relay to operate
t_GOOSERx	GOOSE Transmission and Reception Time	s	Total time for GOOSE message transmission, propagation, and reception
t_logic	Logic Processing Time	s	Time required for internal logic execution in the relay
t_safety	Safety Margin Time	s	Additional time margin added for system uncertainties and safety

Typical Ranges:

Standard urban MV feeder

25–60 ms

High-speed ring-main unit (RMU) scheme

12–22 ms

⚠️ Δt_min ≥ 10 ms for SIL2-certified systems (IEC 61508)

🔧 Open Calculator

GOOSE Message Throughput Limit

N_max = ⌊ T_cycle / (t_tx + t_prop + t_rx) ⌋

Maximum number of concurrent GOOSE messages a relay can process per logic scan without queue overflow.

Variables:

Symbol	Name	Unit	Description
N_max	Maximum Concurrent GOOSE Messages	dimensionless	Maximum number of concurrent GOOSE messages a relay can process per logic scan without queue overflow
T_cycle	Logic Scan Cycle Time	s	Time interval between successive logic scans
t_tx	GOOSE Message Transmission Time	s	Time required to transmit a single GOOSE message
t_prop	Propagation Delay	s	Signal propagation delay across the network
t_rx	GOOSE Message Reception and Processing Time	s	Time required for the relay to receive and process a single GOOSE message

Typical Ranges:

Class A relay (IEC 61850-8-1)

8–16 messages/cycle

Class B relay (high-availability)

24–40 messages/cycle

⚠️ N_actual ≤ 0.7 × N_max to accommodate burst traffic during faults

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🏭 Engineering Example

San Diego Gas & Electric (SDG&E) Miramar Substation Upgrade

N/A — Electrical infrastructure application

Logic Cycle Time

3.1 ms

Trip Logic Delay

45 ms

Blocking Hold-off Time

120 ms

Zone Boundary CT Ratio

1200:5 A

GOOSE Latency (measured)

8.2 ms

🏗️ Applications

Automatic Fault Isolation in Smart Distribution Grids
Microgrid Seamless Transfer Protection
Industrial Process Power System Segregation

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📋 Real Project Case

Data Center Tier IV Electrical System Protection Coordination

42 MW hyperscale data center in Northern Virginia

Challenge: Need for zero downtime during faults while maintaining selective tripping across 4-level distributio...

_up − T_down = 0.42 sGOOSE Latency BudgetMU + Switch + Relay = 38 ms•Bus-tie logic

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🎨 Technical Diagrams

📚 References

[1]

IEEE Guide for Application of Digital Line Current Differential Relaying — IEEE Power & Energy Society

[2]

IEC 61850-7-420: Communication networks and systems for power utility automation – Part 7-420: Basic communication structure – Distributed energy resources logical nodes — International Electrotechnical Commission

[3]

NERC Reliability Standard CIP-010-4: Cyber Security – Electronic Security Perimeter(s) — North American Electric Reliability Corporation

[4]

Siemens SIPROTEC 5 Application Manual – Logic Interlocking — Siemens Energy AG

🔗 Related Knowledge

Microgrid Islanding Detection and Protection Coordination IEC 61850 GOOSE-Based Coordination Messaging Architecture Coordination Failure Root Cause Analysis: 12 Common Pitfalls