Time-Current Coordination for Arc Flash Reduction: Relay Settings & Trip Delay Optimization

Typical Arc Flash Reduction

60–95% energy reduction achievable via optimized TCC + ZSI

Key Standards

IEEE 1584-2018, NFPA 70E-2024, IEEE C37.112-2018

Minimum Validated Trip Time

0.017 s (1 cycle at 60 Hz) — practical limit for microprocessor relays

PPE Impact

Reducing incident energy from 25 → 4 cal/cm² drops required PPE from Category 4 to Category 2

⚠️ Why It Matters

1

Inadequate coordination margin

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2

Upstream breaker trips before downstream device clears fault

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3

Arcing duration extends from 0.02 s to >0.5 s

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4

Incident energy increases 3–10× (quadratic dependence on time)

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5

PPE requirements escalate from Category 2 to Category 4+

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6

Worker safety exposure risk rises disproportionately

📘 Definition

Time-Current Coordination (TCC) for arc flash reduction is the systematic selection and verification of protective device time-current characteristics to ensure selective clearing of faults while minimizing incident energy at downstream equipment. It integrates relay pickup settings, time dial/multiplier settings, instantaneous overrides, and zone-selective interlocking (ZSI) to enforce a defined coordination margin (e.g., 0.1–0.3 s) between upstream and downstream devices. The objective is to reduce arcing time — the dominant variable in IEEE 1584 incident energy calculations — without compromising system selectivity or reliability.

🎨 Concept Diagram

AI-generated illustration for visual understanding

💡 Engineering Insight

Never optimize relay settings solely for speed — the most effective arc flash reduction occurs when you *constrain* the fastest possible trip time to the *minimum necessary* to maintain coordination. For example, reducing arcing time from 0.25 s to 0.05 s yields massive energy reduction, but dropping further to 0.02 s often violates coordination at adjacent buses and introduces nuisance tripping. Real-world reliability trumps theoretical minima.

📖 Detailed Explanation

Time-Current Coordination begins with understanding how overcurrent devices respond to fault current magnitude: higher current causes faster tripping. Electromechanical and digital relays follow standardized inverse-time curves (e.g., IEEE C37.112 Very Inverse, Extremely Inverse), where operating time decreases nonlinearly as fault current increases above pickup. This behavior allows engineers to 'stack' trip curves — ensuring downstream devices always trip before upstream ones for the same fault.

The arc flash hazard depends critically on *how long* the arc sustains — not just fault current magnitude. Because incident energy E ∝ I² × t, halving arcing time reduces energy more than doubling fault current raises it. Thus, coordination isn’t just about selectivity — it’s an energy optimization problem. Modern digital relays enable dual-element protection: an instantaneous function for high-magnitude arcs near the device, and a precisely tuned time-delayed element for lower-magnitude, longer-duration faults farther away.

Advanced applications integrate communication-assisted schemes like Zone Selective Interlocking (ZSI) and bus differential protection. ZSI allows downstream relays to send a restraint signal to upstream relays upon detecting local fault current — effectively collapsing the upstream time delay to near-zero *only when needed*. This achieves sub-cycle (<0.017 s) clearing at the source while maintaining full coordination during through-faults. Such techniques are now mandated in NFPA 70E 2024 Annex D.10 for new installations with incident energy >8 cal/cm².

🔄 Engineering Workflow

Step 1

Step 1: Collect one-line diagram, device ratings, and available fault currents (from utility or ETAP/ SKM study)

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Step 2

Step 2: Model protective devices using manufacturer TCC curves (e.g., Eaton, Siemens, SEL) in coordination software (ETAP, EasyPower, or ARCAD)

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Step 3

Step 3: Perform iterative relay setting optimization — prioritize arcing time reduction at highest-risk locations (e.g., 480 V panels, MCCs) while preserving coordination margins

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Step 4

Step 4: Validate settings against minimum arc flash incident energy targets (e.g., ≤1.2 cal/cm² for ‘no PPE’ zones per NFPA 70E Table 130.7(C)(15)(a))

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Step 5

Step 5: Conduct commissioning tests: secondary injection, relay timing verification, and ZSI functional test

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Step 6

Step 6: Document final settings, TCC plots, arc flash labels, and update system studies annually or after major modifications

📋 Decision Guide

Rock/Field Condition	Recommended Design Action
Downstream MCC with 400 A molded-case breaker (instantaneous @ 8×), upstream 1200 A relay (SEL-751)	Set relay I_inst = 3200 A (8×400 A) + 20% margin; TDS = 2.0; verify Δt ≥ 0.2 s at 12 kA bolted fault
Critical 4.16 kV motor control center fed from utility substation with 500 MVA available short-circuit	Install ZSI between primary and secondary relays; use I_inst override at 12 kA, time-delayed element set to clear in ≤0.08 s at 3× pickup
Legacy electromechanical relays (CO-8, CO-9) with limited TDS resolution and no I_inst	Replace with digital relays (e.g., Schweitzer Engineering SEL-351S) featuring dual-set instantaneous elements and programmable TCC curves

📊 Key Properties & Parameters

Arcing Time (t_arc)

0.02–2.0 s (for 600 V–38 kV systems with standard OCPDs)

Duration from arc initiation until current interruption by the nearest overcurrent protective device

⚡ Engineering Impact:

Directly squared in IEEE 1584 incident energy equation — reducing t_arc from 0.5 s to 0.1 s cuts energy by 96%.

Coordination Margin (Δt)

0.1–0.3 s (per NFPA 70E Annex D & IEEE C37.100.1)

Minimum time separation required between the trip curves of two cascaded protective devices to guarantee selectivity under worst-case fault current

⚡ Engineering Impact:

Margins <0.1 s risk nuisance coordination loss; >0.3 s unnecessarily increases downstream arc flash energy.

Relay Instantaneous Pickup (I_inst)

3–15× pickup current (I_pickup) or 2–12 kA (for 480 V–15 kV feeder relays)

Minimum current magnitude at which an overcurrent relay initiates immediate tripping, bypassing intentional time delay

⚡ Engineering Impact:

Too low causes false tripping on motor inrush; too high defeats arc flash mitigation by forcing reliance on slower time-delayed elements.

Time Dial Setting (TDS)

0.5–12.0 (unitless, per IEEE C37.112-2018)

Adjustable parameter in inverse-time overcurrent relays that scales the operating time along the IEC/IEEE standard time-current curve

⚡ Engineering Impact:

Each 1.0 increment changes trip time by ~2–4× at 10× pickup — critical for fine-tuning arc flash response without violating coordination.

📐 Key Formulas

IEEE 1584 Incident Energy

E = k₁ × k₂ × log₁₀(Iₐ) × t × [0.0016 × G⁻⁰·⁹⁸³]

Empirical calculation of arc flash incident energy (cal/cm²) at working distance

Variables:

Symbol	Name	Unit	Description
E	Incident Energy	cal/cm²	Arc flash incident energy at working distance
k₁	Equipment Constant	dimensionless	Constant based on equipment type (open or box)
k₂	Grounding Constant	dimensionless	Constant based on system grounding (ungrounded/high-impedance vs grounded)
Iₐ	Arc Current	kA	RMS arc current in kiloamperes
t	Arc Duration	s	Duration of the arc in seconds
G	Gap Distance	mm	Distance between electrodes in millimeters

Typical Ranges:

480 V panelboard, 25 mm gap

1.2–40 cal/cm²

4.16 kV switchgear, 152 mm gap

5–120 cal/cm²

⚠️ ≤1.2 cal/cm² permits no PPE per NFPA 70E Table 130.7(C)(15)(a)

🔧 Open Calculator

Coordination Margin

Δt = t_upstream − t_downstream

Minimum time difference between upstream and downstream device clearing times at identical fault current

Variables:

Symbol	Name	Unit	Description
Δt	Coordination Margin	s	Minimum time difference between upstream and downstream device clearing times at identical fault current
t_upstream	Upstream Device Clearing Time	s	Time required for the upstream protective device to clear a fault
t_downstream	Downstream Device Clearing Time	s	Time required for the downstream protective device to clear a fault