๐Ÿ“‹ Case Study

Hospital Emergency Power System Arc Flash Hazard Mapping

Critical life-safety circuits required live work during emergencies; existing labels omitted generator contribution to arc current

๐Ÿ—๏ธ Project Overview

Urban Level I trauma center with dual 12.47 kV emergency feeders and paralleled 2.4 kV generators

๐ŸŽฏ Challenge

Critical life-safety circuits required live work during emergencies; existing labels omitted generator contribution to arc current

๐Ÿ”ง Design Approach

Performed combined utility + generator fault contribution analysis; modeled worst-case arc duration using generator X/R and breaker coordination

๐Ÿ“ Design Diagram

Hospital Emergency Power System Arc Flash Hazard Mapping UTILITY I_utility GENERATOR I_gen MAIN BUS FAULT POINT Arc Duration: 1.82 s Incident Energy: 34.9 cal/cmยฒ I_gen / I_total = 0.37 Live Work Risk IEEE 1584-2023 Multi-Source Model Utility Generator Hazard

AI-generated project design illustration

๐Ÿ“ Key Calculations

Generator Contribution Factor

I_gen / (I_utility + I_gen)
Result: 0.37
Increased total arc current by 37%

Arc Duration with Generator

Breaker trip time at 37% reduced current
Result: 1.82 s
Extended duration increased IE quadratically

IE with Generator Inclusion

IEEE 1584-2023 multi-source model
Result: 34.9 cal/cmยฒ
Required Category 3 PPE even at 2.4 kV

๐Ÿ“Š Results

Redesigned labeling included 'GEN IN SERVICE' warning flags; implemented automatic generator isolation interlock for non-emergency maintenance; reduced average incident energy by 41% across 22 critical panels

๐Ÿ’ก Lessons Learned

  • โ€ขGenerator contribution must be modeled for both magnitude AND duration effects
  • โ€ขLife-safety systems demand dual-layer hazard communication (label + procedure)
  • โ€ขInterlocks must be tested under simulated low-voltage, high-impedance arc conditions

โœ… Key Takeaways

  • 1Generator contribution must be modeled for both magnitude AND duration effects
  • 2Life-safety systems demand dual-layer hazard communication (label + procedure)
  • 3Interlocks must be tested under simulated low-voltage, high-impedance arc conditions